1. Field of the Invention
The present invention relates to a semiconductor device having a ferroelectric capacitor and a method of manufacturing such a device.
2. Description of the Related Art
A ferroelectric memory is known as a non-volatile semiconductor memory utilizing a polarization of its ferroelectric material exhibiting a hysteresis against an applied electric field. The ferroelectric memory has characteristics of a short operation time for writing and reading and a low driving voltage. By utilizing these characteristics, the ferroelectric memory can replace not only a prior non-volatile semiconductor memory such as EEPROM, but also a volatile semiconductor memory such as DRAM. Research on the ferroelectric memory has, therefore, been conducted.
The ferroelectric memory has a plurality of memory cells. The memory cell includes a ferroelectric capacitor (hereinafter referred to as capacitor) having a ferroelectric layer sandwiched by a lower electrode layer and an upper electrode layer.
The capacitor comprises a multilayer structure body including a lower electrode layer consisting of, for example, platinum (Pt), a ferroelectric layer consisting of a ferroelectric material such as lead zirconate titanate (PZT) and an upper electrode layer consisting of platinum (Pt) in this order. The above multilayer structure body is covered with a protective layer consisting of silicon dioxide (SiO2) formed by CVD and is protected. For example, refer to Japanese Patent Kokai No. 09-121023.
In a process for forming the protective layer, a hydride gas such as silane is utilized as a material of the protective layer. The hydride gas is decomposed to generate a hydrogen gas during formation of the protective layer. If the hydrogen gas diffuses into the ferroelectric layer, the ferroelectric layer is deteriorated by the reducing reaction. The deteriorated ferroelectric layer does not have satisfactory electrical properties. Thus, it is proposed to provide a protective layer to a capacitor as a hydrogen diffusion preventing layer consisting of tantalum oxide. For example, refer to Japanese Patent Kokai No. 2002-353414.
The memory cell comprises a capacitor electrically connected to a switch element such as a transistor.
The above memory cell including a capacitor is formed on a silicon substrate having a MOS type transistor thereon. The MOS type transistor is covered with an interlayer insulating film. The capacitor comprises a lower electrode layer, a ferroelectric layer and an upper electrode layer, which are formed in this order on the interlayer insulating film. The capacitor is covered with a protective layer. The protective layer is also provided on the interlayer insulating film outside a region where the capacitor is mounted.
A contact hole for the upper electrode layer of the capacitor is applied to the protective layer so as to expose the upper electrode layer. Further, a source/drain contact hole is formed so as to pass through the protective layer and the interlayer insulating film, and exposes a source/drain region of the MOS type transistor. A connection wiring electrically connects the upper electrode layer to the source/drain region through the contact hole for the upper electrode layer and the contact hole for the source/drain area, to electrically connect the capacitor to the MOS type transistor.
The ferroelectric memory including the memory cell such as the above construction can be used as a memory of a logic LSI because of its speed and low power driving. For example, refer to “TOWARD PRACTICAL APPLICATION OF A FeRAM HYBRID LSI”, Advanced Process of a ferroelectric memory, ver. 1, pp. 244-246, published by Science Forum on Sep. 13, 1999.
A FeRAM hybrid LSI which mixedly mounts the ferroelectric memory (hereinafter referred to as hybrid LSI) has a memory area and a logic area. In the memory area, switch elements such as a MOS type transistor and capacitors connected to the switch element are formed. In the logic area, a logic circuit is formed from logic circuit elements such as a CMOS.
The memory area has the same construction as the above ferroelectric memory. The switch element and the capacitor are connected to each other through a contact hole formed in an interlayer insulating layer covering the switch element and a protect layer covering the capacitor.
A logic circuit element formed on a substrate and an interlayer insulating layer covering the logic circuit element are formed in the logic area. A protect layer covering the capacitor is formed on the interlayer insulating layer. A contact hole for the logic circuit element is formed so as to pass through the interlayer insulating layer and the protect layer, and exposes a source/drain area of the logic circuit element. A logic circuit wiring is formed to connect the logic circuit elements to each other through the contact hole for the logic circuit element.